Below shown various GATEs with their VHDL code... <!-------------------------------------------->
| AND Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in AND sig_2_in; |
| OR Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in OR sig_2_in; |
| NOT Gate | VHDL Code |
|---|---|
|
|
sig_2_out <= NOT sig_1_in; |
| NAND Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in NAND sig_2_in; |
| NOR Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in NOR sig_2_in; |
| XOR Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in XOR sig_2_in; |
| XNOR Gate | VHDL Code |
|---|---|
|
|
sig_3_out <= sig_1_in XNOR sig_2_in; |
<!-------------------------------------------->







